When a super-scalar processor and/or a VLIW processor is employed in a computer or a data processor, a plurality of memory accesses during one cycle depending on cases. To conduct a plurality of memory access operations during one cycle, it is necessary to use memory ports as many as there are memory accesses during one cycle. A conventional example of a dual-port memory capable of conducting a plurality of memory accesses during one memory cycle has been described in pages 168 to 170 of an article "Power and PowerPC" published from Morgan Kaufmann Publishers, Inc. in 1994.
In accordance with a first method, there is used a memory including memory cells which can be accessed via two ports. For one memory cell in which information of one bit is stored, there are disposed two sets of address decoders, two sets of word lines, two sets of data bit lines, and two sets of sense amplifiers. This leads to a memory which can be accessed via two ports. The first method requires two sets of work lines and data bit lines. When compared with the single-port configuration, the memory cell area is doubled to implement the memory having the same memory capacity.
In a second method, the conventional single-port memory is disposed in a duplicated constitution to implement a memory which can be accessed via two ports. When compared with the dual-port memory of the first embodiment, this memory differs in that the memory cells are also duplicated. Consequently, to write data in the memory, the same data is required to be written in both memory areas at the same address. Since the memory cells are duplicated in the second method, the capacity of the necessary memory cells is two times that of the inherent memory. In other words, only one half of the actual memory cells can be used to store independent data. Namely, for the same memory capacity, the area of memory cells is doubled when compared with the prior art.
Between the first method and the second method, there exists only quite a small difference in the memory cell area. Additionally, in the first method using the memory cells in a shared manner, when the memories are accessed at the same address via two ports, one of the accesses is set to a wait state and hence the access time inevitably becomes doubled.
In a third method, the memory is subdivided into two memory banks in accordance with addresses. In an operation to access two memory banks, the accesses are simultaneously processed. Data at an address exists only in either one of the memory banks. Consequently, when compared with the dual-port memory, there is required a selector for each of an address input section and a data output section to establish a correspondence between the memory ports and the memory banks. In this connection, the lower-most bit of the accessing address is used to indicate the selection for the selector.
Since the memory cells are not duplicated in the third method, the capacity of memory cells indicates the inherent memory capacity. When compared with the second method, the memory capacity is doubled with the same number of memory cells. However, the memory bank to be accessed is determined by one bit of the address in the third method, the total memory access time includes, in addition to the memory access time, the selection time of the selector. In consequence, there is a fear of elongation of the total memory access time when compared with the second method.
In a fourth method, one single-port memory is used in a time-shared fashion. One cycle is subdivided into two sections in which a first-half cycle is used for an access via a first memory port and a second-half cycle is utilized for an access via a second memory port to thereby implement a dual-port memory.
Since the memory cells and the like are not duplicated in the fourth method, the capacity of memory cells directly indicates the inherent memory capacity like in the third method. However, to execute two memory access operations during one cycle, the memory access operation is required to be increased, i.e., the memory cell access time is required to be reduced to half that of the original access time. Conversely, when the memory cell access time is used as the reference (when the access time is kept unchanged), the total cycle time is to be doubled to achieve two memory access operations during one cycle.
The conventional multi-port memory described above is attended with the following problems. When the memory cell area is kept retained, the memory capacity is lowered to half that of memory cells or the memory access time becomes longer. Alternatively, when the memory cell access time is used as the criterion, the total cycle time is to be doubled.
It is therefore an object of the present invention, which solves the problems above, to provide a multi-port memory in which the memory capacity is substantially equal to that of memory cells in the single-port memory and a plurality of memory access operations can be simultaneously executed substantially without elongating the memory access time, without causing a bank access collision, and without increasing the total cycle time.